VISC architecture

In computing, VISC (Virtual Instruction Set Computing) architecture is a processor instruction set architecture and microarchitecture developed by Soft Machines,^[1][2][3][4] which uses the Virtual Software Layer (translation layer) to dispatch a single thread of instructions to the Global Front End which splits instructions into virtual hardware threadlets which are then dispatched to separate virtual cores. These virtual cores can then send them to the available resources on any of the physical cores. Multiple virtual cores can push threadlets into the reorder buffer of a single physical core, which can split partial instructions and data from multiple threadlets through the execution ports at the same time. Each virtual core keeps track of the position of the relative output. This form of multithreading can increase single threaded performance by allowing a single thread to use all resources of the CPU. The allocation of resources is dynamic on a near-single cycle latency level (1–4 cycles depending on the change in allocation depending on individual application needs. Therefore, if two virtual cores are competing for resources, there are appropriate algorithms in place to determine what resources are to be allocated where.

Unlike the traditional processor designs, VISC doesn't use physical cores, instead the resources of the chip are made available as 'virtual cores' and 'virtual hardware threads' according to workload needs.^[5]

References

This page was last edited on 14 June 2021, at 16:44