The MicroBlaze is a soft microprocessor core designed for Xilinx field-programmable gate arrays (FPGA). As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs.
MicroBlaze was introduced in 2002.[1]
YouTube Encyclopedic
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Creating a MicroBlaze emulator in C++11 (runs Linux!)
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MicroBlaze processor with UART in EDK(Tutorial 1)
Transcription
Suddenly, the music changes. Hi everyone, Though it should be obvious by now, I am creating an emulator in this video. I will try to provide some interesting commentary, so you can better understand what's going on in this video. In the case that you have never bothered to learn how something that is called a 'CPU' works, I will explain it briefly from a programmer's viewpoint. A CPU (Central Processing Unit) is a device that does the following; Step 1: Read an instruction from system memory. The instruction is a numeric value that simply represents an instruction in a manner specified by the CPU's makers. Step 2: Execute the instruction. An instruction might be, for example, 'Add two values together' or 'Read the next instruction from another location' Step 3: Go to step 1. Of course, this was a simplification. There is more to it, but this explains what happens in the code you see on the screen right now. Many of these operations deal with converting numbers to another format, or applying mathematical transformations to them. These shifts, for example, divide or multiply a value by two. Many of simpler programmers have never heard of a concept called 'delay slot'. A delay slot is a CPU feature, where a branch operation is indeed observed by the CPU, but it doesn't take effect immediately. Instead, the CPU processes one or more intermediate instructions first, and /then/ jumps to the address indicated much earlier. The MicroBlaze has one delay slot, but many branch instructions come with a delay slot option. The operation may be delayed, or it may be immediate. The are memory access operations (loading and storing) for different sizes of data. On this architecture, all of them access 32 bits at once, even if they use only a part of it. With MicroBlaze, there are some exceptionally large number of configuration options, that affect what the processor can do and what it cannot do. My emulator implements some of these features listed here, below, or will soon anyway. Sometimes, quite often really, a device attached to the computer requires immediate attention by the operating system running in the computer. This attention request is called an 'interrupt'. When the aptly named interrupt happens, the CPU interrupts whatever it was doing and begins running a code from a special location, where the operating system creators have placed the code to serve the interrupt. When that issue is dealt with, the CPU resumes what it was doing before the interrupt. An example of a matter requiring urgent attention might be when the user moves the mouse cursor and the operating system must let the window system know, so that it can draw the mouse cursor in another spot on the screen. The memory management unit is the core concept behind what makes the processor able to run modern operating systems. With the memory management unit, it is possible to control which areas of memory the programs can read, write or execute and which cannot. It is also what makes techniques like swapping possible. [quiet] Suddenly, music changes again.
Overview
In terms of its instruction set architecture, MicroBlaze is similar to the RISC-based DLX architecture described in a popular computer architecture book by Patterson and Hennessy. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances.
The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, the AXI interconnect, is a system-memory mapped transaction bus with master–slave capability. Older versions of the MicroBlaze used the CoreConnect PLB bus. The majority of vendor-supplied and third-party IP interface to AXI directly (or through an AXI interconnect). For access to local-memory (FPGA RAM), MicroBlaze uses a dedicated LMB bus, which provides fast on-chip storage. User-defined coprocessors are supported through dedicated AXI4-Stream connections. The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module.
Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth (3-stage, 5-stage, or 8-stage), embedded peripherals, memory management unit, and bus-interfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock frequency for reduced logic area. The performance-optimized version expands the execution pipeline to 5 stages, allowing top speeds of more than 700 MHz (on Virtex UltraScale+ FPGA family). Also, key processor instructions which are rarely used but more expensive to implement in hardware can be selectively added/removed (e.g. multiply, divide, and floating point operations). This customization enables a developer to make the appropriate design trade-offs for a specific set of host hardware and application software requirements.
With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the Linux kernel. Otherwise it is limited to operating systems with a simplified protection and virtual memory model, e.g. FreeRTOS or Linux without MMU support. MicroBlaze's overall throughput is substantially less than a comparable hard CPU core (such as the ARM Cortex-A9 in the Zynq).
MicroBlaze V is based on the RISC-V architecture.
Vivado
Xilinx's Vivado Design Suite is the development environment for building current MicroBlaze (or ARM - see Zynq) embedded processor systems in Xilinx FPGAs. Older versions used Xilinx's EDK (Embedded Development Kit) development package.
Designers use the Vivado IP Integrator to configure and build the hardware specification of their embedded system (processor core, memory-controller, I/O peripherals, etc.) The IP Integrator converts the designer's block design into a synthesizeable RTL description (Verilog or VHDL), and automates the implementation of the embedded system (from RTL to the bitstream-file.) For the MicroBlaze core, Vivado generates an encrypted (non human-readable) netlist.
The SDK handles the software that will execute on the embedded system. Powered by the GNU toolchain (GNU Compiler Collection, GNU Debugger), the SDK enables programmers to write, compile, and debug C/C++ applications for their embedded system. Xilinx's tools provides the possibility of running software in simulation, or using a suitable FPGA-board to download and execute on the actual system.
Purchasers of Vivado are granted a perpetual license to use MicroBlaze in Xilinx FPGAs with no recurring royalties. The license does not grant the right to use MicroBlaze outside of Xilinx's devices.
Alternative compilers and development tools have been made available from Altium but an EDK installation and license is still required.
Open source
In June 2009, MicroBlaze became the first soft-CPU architecture to be merged into the mainline Linux kernel source tree. This work was performed by Michal Simek and supported by PetaLogix and Xilinx.
As of September 2009, MicroBlaze GNU tools support is also being contributed to the Free Software Foundation's mainline repositories. Support for MicroBlaze is included in GCC releases starting with version 4.6[2]
Support was added to LLVM in April 2010,[3] but subsequently removed in July 2013[4] due to a lack of maintainer.
Clones
- aeMB, implemented in Verilog, LGPL license
- OpenFire subset, implemented in Verilog, MIT license
- MB-Lite, implemented in VHDL, LGPL license
- MB-Lite+, implemented in VHDL, LGPL license
- myBlaze, implemented in MyHDL, LGPL license
- SecretBlaze, implemented in VHDL, GPL license
Other soft processors
- Nios II
- TSK3000
- Xtensa
- LatticeMico32
- ARC
- RISC-V (A number of open source soft cores are available. At least one is packaged for Vivado.)
- ARM Cortex-M (Cortex-M1 and Cortex-M3 soft cores are available in Vivado)
See also
- OpenCores - a home for many open source soft processor projects
- PicoBlaze
- Advanced Microcontroller Bus Architecture § Advanced eXtensible Interface (AXI)
References
- ^ Xilinx (August 21, 2002). "MicroBlaze RISC 32-Bit Soft Processor datasheet" (PDF).
- ^ "GCC 4.6 Release Series Changes, New Features, and Fixes". 2011-03-15. Retrieved 2011-03-15.
Support has been added for the Xilinx MicroBlaze softcore processor (microblaze-elf) embedded target.
- ^ "LLVM 2.7 Release Notes". releases.llvm.org. Retrieved 2019-04-07.
- ^ Christopher, Eric (2013-07-24). "[LLVMdev] Deprecating and removing the MBlaze backend". Retrieved 2019-04-07.
External links
This page was last edited on 6 January 2024, at 15:29