Transaction-level modeling

Transaction-level modeling (TLM) is an approach to modelling complex digital systems by using electronic design automation software.^[1]: 1955 TLM language (TLML) is a hardware description language, usually, written in C++ and based on SystemC library.^[1] TLMLs are used for modelling where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. It's used for modelling of systems that involve complex data communication mechanisms.^[1]: 1955

Components such as buses or FIFOs are modeled as channels, and are presented to modules using SystemC interface classes. Transaction requests take place by calling interface functions of these channel models, which encapsulate low-level details of the information exchange. At the transaction level, the emphasis is more on the functionality of the data transfers – what data are transferred to and from what locations – and less on their actual implementation, that is, on the actual protocol used for data transfer. This approach makes it easier for the system-level designer to experiment, for example, with different bus architectures (all supporting a common abstract interface) without having to recode models that interact with any of the buses, provided these models interact with the bus through the common interface.^[2]

However, the application of transaction-level modeling is not specific to the SystemC language and can be used with other languages. The concept of TLM first appears in system level language and modeling domain.^[3]

Transaction-level models are used for high-level synthesis of register-transfer level (RTL) models for a lower-level modelling and implementation of system components. RTL is usually represented by a hardware description language source code (e.g. VHDL, SystemC, Verilog).^{[1]: 1955–1957}

History

In 2000, Thorsten Grötker, R&D Manager at Synopsys was preparing a presentation on the communication mechanism in what was to become the SystemC 2.0 standard, and referred to it as "transaction-based modeling". Gilles Baillieu, then a corporate application engineer at Synopsys, insisted that the new term had to contain "level", as in "register-transfer level" or "behavioral level". The fact that TLM does not denote a single level of abstraction but rather a modeling technique didn't make him change his mind. It had to be "level" in order to make it stick. So it became "TLM".^{[citation needed]}

The Open SystemC Initiative was formed to standardize and proliferate the use of the SystemC language. That organization is sponsored by major EDA vendors and customers sharing a common interest in facilitating tool development and IP interoperability. The organization developed the OSCI simulator for open use and distribution.

Since those early days SystemC has been adopted as the language of choice for high level synthesis, connecting the design modeling and virtual prototype application domains with the functional verification and automated path gate level implementation. This offers project teams the ability to produce one model for multiple purposes. At the 2010 DVCon event, OSCI produced a specification of the first synthesizable subset of SystemC for industry standardization.

See also

• Discrete event simulation (DES)
• Event loop
• Event-driven programming
• Message passing
• Reactor pattern vs. Proactor pattern
• Transaction processing
• Asynchronous circuit
• Assembly modelling, for CADs

References

External links

• SystemC.org - SystemC home page.

This page was last edited on 22 May 2023, at 07:32