Circuit underutilization also chip underutilization, programmable circuit underutilization, gate underutilization, logic block underutilization refers to a physical incomplete utility of semiconductor grade silicon on a standardized mass-produced circuit programmable chip, such as a gate array type ASIC, an FPGA, or a CPLD.
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Transcription
Gate array
In the example of a gate array, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.[1]
FPGA
Due to the design components of field-programmable gate array into logic blocks, simple designs that underutilize a single block suffer from gate underutilization, as do designs that overflow onto multiple blocks, such as designs that use wide gates.[2] Additionally, the very generic architecture of FPGAs lends to high inefficiency; multiplexers occupy silicon real estate for programmable selection, and an abundance of flip-flops to reduce setup and hold times, even if the design does not require them,[1] resulting in 40 times less density than of standard cell ASICs.
See also
References
- ^ a b "Chip Design » The Death of the Structured ASIC by Bob Zeidman, president, Zeidman Technologies". chipdesignmag.com. Retrieved 2018-10-07.
- ^ Zilic, Zeljko; Lemieux, Guy; Loveless, Kelvin; Brown, Stephen; Vranesic, Zvonko (June 1995). Designing for High Speed-Performance in CPLDs and FPGAs. CiteSeerX 10.1.1.52.3689.
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This page was last edited on 17 December 2023, at 01:10