College of Engineering

Department of Electrical Engineering and Computer Science

CS61C, Fall 2010

In this assignment, you will implement a 16 bit ALU in logisim. This assignment is an optional lab meant to get you thinking about serious logic design. It will not be graded, but it is *highly* recommended that you complete it. This lab was once a homework assignment that built up to the CPU design project.

The nine functions that you will implement are: add, subtract, OR, AND, shift left logical, shift right logical, shift right arithmetic, set less than, and EQUAL. The ALU will perform a desired function on two 16-bit inputs (X and Y, where x0 is the lowest order bit for x, etc...) and output the result (RESULT). The function will be determined by the value of a control signal (S), as listed below.

In addition to the 16 bits of output provided in RESULT, three additional outputs will be provided: unsigned overflow, signed overflow and equal. Unsigned overflow will have a high value iff the command was an add and unsigned overflow occured. Signed overflow will have a high value iff the command was an add or a subtract, and signed overflow occured. (You need not worry about unsigned overflow for subtractions.) Equal will have a high value when the two inputs are IDENTICAL, and will have a low value at all other times. Notice how the equals signal is generated REGARDLESS of the value of the control signal S.

For the shift instructions detailed below (sll, srl, sra), the shift amount is
*ONLY* the 4 least significant bits of Y. You can ignore the other bits of
Y.

Here's what occurs for each operation:

S | opp | Result |
---|---|---|

000 | or | X | Y |

001 | and | X & Y |

010 | add | X + Y (signal if either type of overflow occurs) |

011 | sub | X - Y (signal if signed overflow occurs) |

100 | sll | X << Y (but logically, don't sign extend!) |

101 | srl | X >> Y (but logically, don't sign extend!) |

110 | sra | X >> Y (but arithmetically, do sign extend!) |

111 | slt | if (X < Y) //Treat X and Y as SIGNED! then result = 1 else result = 0 |

XXX | eq | X == Y (Have this value be on the equals output regardless of selection) |

As we will not be grading this assignment, we obviously cannot enforce any restrictions on which logic blocks you use. In addition, in project 4, you will have no restrictions on what logic blocks you may use. That said, we think you will get the most out of this assignment if, and therefore strongly encourage you to, only use tools from the "Base" and "Gates" libraries in Logisim. You can always strip out your homebrew adder and replace it with a logisim-adder based version if you're feeling nervous about your implementation.

You will not need any items from the Memory library. Your ALU should be stateless. We reserve the right to dock points on project 4 for unjustifiable design decisions.

**LABEL EVERYTHING!**- You can download logisim for yourself as well as view more documentation at the logisim website: http://ozark.hendrix.edu/~burch/logisim/
- You can and
*should*use**multi-bit wires**! Before or after placing a gate you can select the bit width of that gate. This means the number of bits which run through the input and output pins of that gate. For example, a 2 bit wide AND gate with two wires coming in and 1 wire going out actually is taking a**4**bit input and a**2**bit output. The gate performs the one bit AND function on each respective pair of inputs: it ANDs the two lowest order bits and outputs the result on the lowest order bit of the output, etc... The wires will automatically be the width of the input/output pin they are connected to, and Logisim will be kind enough to immediately report any inconsistencies in pins connecting to the same wire. - Please use
**subcircuits**! They make it easier for you, they make it easier for us. Give your subcircuits appropriate labels as well. Keep in mind that Project 4 won't be autograded, and humans will have to look at your schematics (and grade them!). - The key to your sanity on this project is modularity. Don't be afraid to build subcircuits that are multiple levels deep.