The R6000 is a microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS II instruction set architecture (ISA). The chip set consisted of the R6000 microprocessor, R6010 floating-point unit and R6020 system bus controller. The R6000 was the first implementation of the MIPS II ISA.
The R6000 was implemented with emitter-coupled logic (ECL). In the mid- to late 1980s, the trend was to implement high-end microprocessors with high-speed logic such as ECL. As MIPS was a fabless company, the R6000 chip set was fabricated by Bipolar Integrated Technology (BIT) who had acted as a foundry for MIPS since November 1989. However, manufacturing issues that had caused "sporadic deliveries" of the R6000 to MIPS Computer Systems resulted in contractual restrictions being imposed on BIT, preventing the company from supplying other potential customers. Such issues, which had persisted for over a year, were reportedly resolved in 1991, enabling BIT to seek other customers for the product and, as part of its separate licensing agreement with MIPS, to be able to manufacture and sell customised versions of the chip.[1]
The R6000 had few users. Control Data Systems (CDS) used an 80 MHz version in their high-end 4680-300 Series InforServer server. MIPS used the R6000 in their RC6260 and RC6280 servers.[2] One review of the RC6280 published in early 1991 described the product as "the single fastest system we have tested for CPU and FPU performance", enabling a "premium price" to be charged, with such pricing starting from $150,000 for the base configuration. However, delivery times for certain models were estimated at "several months" due to supply uncertainties with the processor.[3]
YouTube Encyclopedic
-
1/1Views:669
-
Roman R6000 Bluetooth Headset Review
Transcription
References
- ^ Ristelhueber, Robert (23 September 1991). "MIPS Lifts Bar on Shipments Of BIT R6000 Microprocessor". Electronic News. p. 18. Retrieved 29 April 2022.
- ^ RC6280 RISComputer (PDF). MIPS Computer Systems Inc. 1989. Retrieved 26 April 2022.
- ^ Wilson, David (January 1991). "Tested Mettle". Unix Review. pp. 71–72, 74–78, 80. Retrieved 29 April 2022.
- "MIPS Chip Set Implements Full ECL CPU". (December 1989). Microprocessor Report. pp. 1, 14–19.
- Horowitz, M. et al. (1990). "A 3.5ns, 1 Watt, ECL register file". ISSCC Digest of Technical Papers, pp. 68–59, 267.
- Roberts, D.; Layman, T.; Taylor, G. (1990). "An ECL RISC microprocessor designed for two level cache". Compcon Spring '90 Digest of Technical Papers, pp. 228–231.
- Thorson, M. (January 1990). "ECL Bus Controller Hits 266 Mbytes/s". Microprocessor Report. pp. 12–13.
This page was last edited on 28 April 2022, at 23:10