Posted write

^[1] A posted write is a computer bus write transaction that does not wait for a write completion response to indicate success or failure of the write transaction. For a posted write, the CPU assumes that the write cycle will complete with zero wait states, and so doesn't wait for the done. This speeds up writes considerably. For starters, it doesn't have to wait for the done response, but it also allows for better pipelining of the datapath without much performance penalty.

A non-posted write requires that a bus transaction responds with a write completion response to indicate success or failure of the transaction, and is naturally much slower than a posted write since it requires a round trip delay similar to read bus transactions.

In reference to memory bus accesses, a posted write is referred to as a posted memory write (PMW).

See also

• CPU cache
• Computer memory

References

• PCI System Architecture, Don Anderson, Tom Shanley, MindShare, Inc - 1999

External links

• Computer hardware buses at Curlie
• Computer hardware buses and slots pinouts with brief descriptions

This page was last edited on 19 December 2021, at 05:36