In electronic low power digital synchronous circuit design, operand isolation is a technique for minimizing the energy overhead associated with redundant operations by selectively blocking the propagation of switching activity through the circuit.[1] This technique isolates sections of the circuit (operation) from "seeing" changes on their inputs (operands) unless they are expected to respond to them. This is usually done using latches at the inputs of the circuit. The latches become transparent only when the result of the operation is going to be used. One can also use multiplexers or simple AND gates instead of latches.
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Mod-01 Lec-30 Minimizing Switched Capacitance - IV
Transcription
Overhead
There is some area overhead associated with this technique since the circuit designer needs to add extra circuitry, i.e. latches, at the inputs. Also, if the latches are being added in a pipeline stage, they might change the critical path, and hence increase the propagation delay and cycle time. In cases where the overhead is not acceptable, one can think of clock gating as an alternative method of low power design.
See also
- Glitch removal
- Clock gating
- Switching losses
- Distributive law - a similar idea in mathematics
- Reduction (mathematics) - a similar idea in mathematics
- Reducing a fraction - a similar idea in mathematics
- Reduced Karnaugh map (RKM) - a similar technique in logic optimization
- Infrequent variables - a similar technique in logic optimization
References
This page was last edited on 4 May 2022, at 17:38