A machine state register (MSR) is one of three process control registers present in the PowerPC processor architecture.
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Transcription
Processors
The implementation details of the machine state register will vary from model to model. Below are two representative implementations, the 32-bit Freescale e200z3 PowerPC core and the 64-bit IBM PowerPC.
e200z3 PowerPC core
Uses of the machine state register
This 32-bit register either controls and/or reports several important processor states.
| Mnemonic | Description |
|---|---|
| UCLE | Enables/disables userspace execution of cache locking instructions |
| SPE | Enables/disables vector instructions |
| WE | Enables/disables power management |
| CE | Enables/disables critical interrupts |
| EE | Enables/disables external interrupts |
| PR | Identifies if the processor is in supervisor or user mode |
| FP | Identifies availability of hardware floating point unit |
| ME | Enables/disables machine check interrupts |
| FE0 | Sets floating point exception mode |
| DE | Enable/disable debug interrupts |
| FE1 | Sets floating point exception mode |
| IS | Sets instruction address space |
| DS | Sets data address space |
Reading and writing the machine state register
The contents of the register may be read using the move from machine state register (mfmsr) instruction and may be modified by executing the return from interrupt (rfi, rfci, rfdi), system call (sc) and move to machine state register (mtmsr) instructions.
PowerPC
Uses of the machine state register
This 64-bit register either controls and/or reports several important processor states.
| Mnemonic | Description |
|---|---|
| SF | Selects 32-bit/64-bit mode |
| HV | Selects hypervisor state |
| EE | Enable/disable external interrupts |
| PR | Selects privileged or problem state |
| FP | Reports floating-point availability |
| ME | Enables/disables machine check interrupts |
| FE0 | Select floating-point mode exception mode |
| SE | Enables/disables single-step tracing |
| BE | Enables/disables branch tracing |
| FE1 | Select floating-point exception mode |
| IR | Enable/disable instruction address translation |
| DR | Enable/disable data address translation |
| PMM | Performance monitor mark |
| RI | Lists whether interrupt is (non-) recoverable |
| LE | Selects Little-Endian or Big-Endian mode (not G5) |
Reading and writing the machine state register
The machine state register can be read using the mfmsr instruction and modified using the mtmsr[d], rfid and hrfid instructions.
Confusion with model-specific register
While the machine state register found in the PowerPC architecture and the model-specific registers found in IA-32 and x86-64 architectures fulfill similar functions and the initialism "MSR" can refer to either, there are important differences that distinguish them. The machine state register, a single register, provides coarse-grained control over a small number of machine functions. In contrast, dozens to hundreds of model-specific registers exist on recent IA-32 and x86_64 architectures and provide a much finer granularity of both reporting and control of machine state. The term "machine state register" does not appear in Intel and AMD documentation; likewise "model-specific register" does not appear in IBM and Freescale documentation.
References
- UM0434 e200z3 PowerPC core reference manual, Rev. 1, May, 2007
- AIX 6.1 Assembler Language Reference
- PowerPC Operating Environment Architecture, Book III, v2.02, Jan 28 2005
- Freescale PowerPC Architecture Primer Rev 0.1, Jun 2005
This page was last edited on 14 July 2022, at 12:31