Junction-Less nanowire transistor (JLNT) is a type of Field-effect transistor (FET) in which the channel consists of one or more nanowires and does not contain a junction.
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Transcription
Existing devices
Multiple JLNT devices were manufactured in various labs:
Tyndall National Institute in Ireland
JLT is a nanowire-based transistor that has no gate junction.[1] (Even MOSFET has a gate junction, although its gate is electrically insulated from the controlled region.) Junctions are difficult to fabricate, and, because they are a significant source of current leakage, they waste significant power and heat. Eliminating them held the promise of cheaper and denser microchips. The JNT uses a simple nanowire of silicon surrounded by an electrically isolated "wedding ring" that acts to gate the flow of electrons through the wire. This method has been described as akin to squeezing a garden hose to gate the flow of water through the hose. The nanowire is heavily n-doped, making it an excellent conductor. Crucially the gate, comprising silicon, is heavily p-doped; and its presence depletes the underlying silicon nanowire thereby preventing carrier flow past the gate.
LAAS
A Junction-Less Vertical Nano-Wire FET (JLVNFET) manufacturing process was developed in Laboratory for Analysis and Architecture of Systems (LAAS).[2]
Electrical Behaviour
Thus the device is turned off not by reverse bias voltage applied to the gate, as in the case of conventional MOSFET but by full depletion of the channel. This depletion is caused due to work-function difference (Contact_potentials) between the gate material and doped silicon in the nanowire.
The JNT uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance.[3]
Germanium has been used instead of silicon nanowires.[4]
References
- ^ Kranti, A.; Yan, R.; Lee, C. -W.; Ferain, I.; Yu, R.; Dehdashti Akhavan, N.; Razavi, P.; Colinge, J. P. (2010). "Junctionless nanowire transistor (JNT): Properties and design guidelines". 2010 Proceedings of the European Solid State Device Research Conference. p. 357. doi:10.1109/ESSDERC.2010.5618216. ISBN 978-1-4244-6658-0.
- ^ Larrieu, Guilhem; Han, X.-L. (2013). "Vertical nanowire array-based field effect transistors for ultimate scaling". Nanoscale. 5 (6): 2437–2441. Bibcode:2013Nanos...5.2437L. doi:10.1039/c3nr33738c. eISSN 2040-3372. ISSN 2040-3364. PMID 23403487.
- ^ Colinge, J. P.; Kranti, A.; Yan, R.; Lee, C. W.; Ferain, I.; Yu, R.; Dehdashti Akhavan, N.; Razavi, P. (2011). "Junctionless Nanowire Transistor (JNT): Properties and design guidelines". Solid-State Electronics. 65–66: 33–37. Bibcode:2011SSEle..65...33C. doi:10.1016/j.sse.2011.06.004. S2CID 8382657.
- ^ Yu, Ran (2013). "Junctionless nanowire transistor fabricated with high mobility Ge channel". Physica Status Solidi RRL. 8: 65–68. doi:10.1002/pssr.201300119. S2CID 93197577.
Junctionless Nanowire Transistor: Properties and Device Guidelines
Ferain Junctionless Transistors (pdf)
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This page was last edited on 3 December 2023, at 15:55