A hardware verification language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language. HVLs typically include features of a high-level programming language like C++ or Java as well as features for easy bit-level manipulation similar to those found in HDLs. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification.
SystemVerilog, OpenVera, e, and SystemC are the most commonly used HVLs. SystemVerilog attempts to combine HDL and HVL constructs into a single standard.
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Functional Hardware Verification: Introduction
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SOC VERIFICATION WITH SYSTEM VERILOG. INTERFACES by Ramdas Mozhikunnath
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SOC VERIFICATION WITH SYSTEM VERILOG. BLOCKS by Ramdas Mozhikunnath
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See also
- OpenVera
- e
- SystemC
- SystemVerilog
- Property Specification Language
- Python with cocotb
- Scala with ChiselTest
References
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This page was last edited on 22 August 2023, at 12:52