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Nvidia Drive

From Wikipedia, the free encyclopedia

Nvidia Drive is a computer platform by Nvidia, aimed at providing autonomous car and driver assistance functionality powered by deep learning.[1][2] The platform was introduced at the Consumer Electronics Show (CES) in Las Vegas in January 2015.[3] An enhanced version, the Drive PX 2 was introduced at CES a year later, in January 2016.[4]

The closely platform related software release program at some point in time was branded NVIDIA DRIVE Hyperion along with a revision number helping to match with the generation of hardware it is created for - and also creating ready to order bundles under those term. In former times there were only the terms Nvidia Drive SDK for the developer package and sub-included Nvidia Drive OS for the system software (aka OS) that came with the evaluation platforms or could be downloaded for OS switching and updating later on.

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  • NVIDIA DRIVE Autonomous Vehicle Platform
  • GTC 2015: NVIDIA DRIVE PX Self-Driving Car Computer and Deep Learning (part 8)

Transcription

Hardware and semiconductors

Maxwell based

The first of Nvidia's autonomous chips was announced at CES 2015, based on the Maxwell GPU microarchitecture.[5] The line-up consisted of two platforms:

Drive CX

The Drive CX was based on a single Tegra X1 SoC (System on a Chip) and was marketed as a digital cockpit computer, providing a rich dashboard, navigation and multimedia experience. Early Nvidia press releases reported that the Drive CX board will be capable of carrying either a Tegra K1 or a Tegra X1.[6]

Drive PX

Drive PX

The first version of Drive PX is based on two Tegra X1 SoCs, and was an initial development platform targeted at (semi-)autonomous driving cars.

Pascal based

Drive PX platforms based on the Pascal GPU microarchitecture were first announced at CES 2016.[7] This time only a new version of Drive PX was announced, but in multiple configurations.

Drive PX 2

The Nvidia Drive PX 2 is based on one or two Tegra X2 SoCs where each SoC contains 2 Denver cores, 4 ARM A57 cores and a GPU from the Pascal generation.[8] There are two real world board configurations:

  • for AutoCruise: 1× Tegra X2 + 1 Pascal GPU
  • for AutoChauffeur: 2× Tegra X2 + 2 Pascal GPU's

There is further the proposal from Nvidia for fully autonomous driving by means of combining multiple items of the AutoChauffeur board variant and connecting these boards using e.g. UART, CAN, LIN, FlexRay, USB, 1 Gbit Ethernet or 10 Gbit Ethernet. For any derived custom PCB design the option of linking the Tegra X2 Processors via some PCIe bus bridge is further available, according to board block diagrams that can be found on the web.

All Tesla Motors vehicles manufactured from mid-October 2016 include a Drive PX 2, which will be used for neural net processing to enable Enhanced Autopilot and full self-driving functionality.[9] Other applications are Roborace.[10] Disassembling the Nvidia-based control unit from a recent Tesla car showed that a Tesla was using a modified single-chip Drive PX 2 AutoCruise, with a GP106 GPU added as a MXM Module. The chip markings gave strong hints for the Tegra X2 Parker as the CPU SoC.[11][12]

Volta based

Systems based on the Volta GPU microarchitecture were first announced at CES 2017[13]

Drive PX Xavier

The first Volta based Drive PX system was announced at CES 2017 as the Xavier AI Car Supercomputer.[13] It was re-presented at CES 2018 as Drive PX Xavier.[14][15] Initial reports of the Xavier SoC suggested a single chip with similar processing power to the Drive PX 2 Autochauffeur system.[16] However, in 2017 the performance of the Xavier-based system was later revised upward, to 50% greater than Drive PX 2 Autochauffeur system.[13] Drive PX Xavier is supposed to deliver 30 INT8 TOPS of performance while consuming only 30 watts of power.[17] This spreads across two distinct units, the iGPU with 20 INT8 TOPS as published early and the somewhat later on announced, newly introduced DLA that provided an additional 10 INT8 TOPS.

Drive PX Pegasus

In October 2017 Nvidia and partner development companies announced the Drive PX Pegasus system, based upon two Xavier CPU/GPU devices and two post-Volta (Turing) generation GPUs. The companies stated the third generation Drive PX system would be capable of Level 5 autonomous driving, with a total of 320 INT8 TOPS of AI computational power and a 500 Watts TDP.[18][19]

Ampere based

Drive AGX Orin

The Drive AGX Orin board family was announced on December 18, 2019, at GTC China 2019.[20] On May 14, 2020, Nvidia announced that Orin would be utilizing the new Ampere GPU microarchitecture and would begin sampling for manufacturers in 2021 and be available for production in 2022.[21] Follow up variants are expected to be further equipped with chip models and/or modules from the Tegra Orin SoC.

Ada Lovelace based

DRIVE Atlan (Cancelled)

Nvidia announced the SoC codenamed Atlan on April 12, 2021 at GTC 2021.[22]

Nvidia announced the cancellation of Atlan on September 20, 2022, which was supposed to be equipped with a Grace-Next CPU, and an Ada Lovelace based GPU, and Nvidia announced that their next SoC was called Thor.[23]

Blackwell based

DRIVE Thor

Announced on September 20, 2022,[24] Nvidia DRIVE Thor comes equipped with an Arm Neoverse V3AE CPU,[25] and a Blackwell based GPU, which was announced on March 18, 2024.[26]

Software and bundling

With the label Hyperion[27] added to their reference platform[28] series Nvidia promotes their mass products so that others can easily test drive and then create their own automotive grade products on top. Especially the feature rich software part of the base system is meant to be a big help for these others to quickly go ahead into developing their application specific solutions. Third-party companies, such as DeepRoute.ai, have publicly indicated using these software platform as their base of choice.[29] The whole design is concentrating on UNIX/Posix compatible or derived runtime environments (Linux,[30] Android,[31] QNX - aka the Drive OS variants) with special support for the semiconductors mentioned before in form of internal (CUDA, Vulkan) and external support (special interfaces and drivers for camera, lidar, CAN and many more) of the respective reference boards. For clearness Nvidia bundles the core of the developer needed software as Drive SDK that is sub-divided into DRIVE OS, DriveWorks, DRIVE AV, and DRIVE IX components.[32]

Hyperion
Version 		Announced Latest
Chip Launch 		Start of
Road Usage 		Target Use Case Semiconductors Reference Platforms / Developer Kits Drive OS Version Sensor Support
7.1[33] 2020 Level 2+ autonomous driving Xavier, Turing GPU DRIVE AGX Xavier Developer Kit,
DRIVE AGX Pegasus Developer Kit 		vehicle external: 7x camera, 8x radar;
vehicle internal: 1x camera
8[34][30] 2020 Xavier, Turing GPU DRIVE™ AGX Pegasus GV100,
DRIVE™ AGX Xavier 		5.0.13.2 (linux) vehicle external: 12x camera, 9x radar, 1x lidar
8.1[35] 2022 estimated for 2024 Orin, Xavier, Turing GPU NVIDIA DRIVE AGX Orin™,
DRIVE AGX Pegasus,
DRIVE Hyperion 8.1 Developer Kits[36] 		Orin: 6.0 (latest: 6.0.4)
Xavier/Pegasus:5.2.6[32] 		vehicle external: 12x camera, 9x radar, 1x lidar
9[37][38] March 2022 2024 estimated for 2026 Atlan (Cancelled) vehicle external: 14x camera, 9x radar, 3x lidar, 20x ultrasonic;
vehicle internal: 3x camera, 1x radar

Note: As of now the above table is still 'fresh' and thus might be incomplete.

Reference board comparison

Nvidia provided
reference board 		Drive CX Drive PX Drive PX 2

(AutoCruise)

Drive PX 2

(Tesla)

Drive PX 2

(AutoChauffeur)

Drive PX 2

(Tesla 2.5)

Drive PX Xavier[15] Drive PX Pegasus[39] Drive AGX Orin[20] Drive AGX Pegasus OA[40] Drive Atlan (Cancelled) Drive Thor
GPU Microarchitecture Maxwell (28 nm) Pascal (16 nm) Volta (12 nm) Ampere (8 nm[41]) Ada Lovelace (TSMC 4N) Blackwell (TSMC 4NP[42])
Announced January 2015 September 2016[43] October 2016[44] January 2016 August 2017[45] January 2017 October 2017 December 2019 April 2021[46] September 2022[47]
Launched N/A N/A N/A N/A N/A N/A N/A 2022[48] Cancelled[49] 2025[47]
Chips 1x Tegra X1 2x Tegra X1 1x Tegra X2 (Parker)

+ 1x Pascal GPU

2x Tegra X2 (Parker)

+ 2x Pascal GPU

2x Tegra X2 (Parker)

+ 1x Pascal GPU[50]

1x Tegra Xavier[51] 2x Tegra Xavier

+ 2x Turing GPU

2x Tegra Orin 2x Tegra Orin

+ 2x Ampere GPU

?x Grace-Next CPU[46]

+ ?x Ada Lovelace GPU[52]

?x Arm Neoverse Poseidon AE CPU[53]

+ ?x Blackwell GPU[54]

CPU 4x Cortex A57

4x Cortex A53

8x Cortex A57

8x Cortex A53

2x Denver

4x Cortex A57

4x Denver

8x Cortex A57

4x Denver

8x Cortex A57

8x Carmel ARM64[51] 16x Carmel ARM64 12x Cortex A78AE 24x Cortex A78AE ?x Grace-Next[46] ?x Arm Neoverse Poseidon AE[55]
GPU 2 SMM Maxwell

256 CUDA cores

4 SMM Maxwell

512 CUDA cores

1x Parker GPGPU

(1x 2 SM Pascal,
256 CUDA cores)

1x Parker GPGPU

(1x 2 SM Pascal,
256 CUDA cores
on a MXM slot[11])

2x Parker GPGPU

(2x 2 SM Pascal,
512 CUDA cores)
+ 2x dedicated MXM modules[56]

1x Parker GPGPU

1x 2 SM Pascal,
256 CUDA cores [45][50]

1x Volta iGPU

(512 CUDA cores)[51]

2x Volta iGPU

(512 CUDA cores)
2x Turing dGPUs
(? CUDA cores)

2x Ampere iGPU

(?CUDA cores)

2x Ampere iGPU

(? CUDA cores)
2x Ampere dGPU
(? CUDA cores)

?x Ada Lovelace[57] ?x Blackwell GPU[58]
Accelerator 1x DLA

1x PVA[51]

2x DLA

2x PVA

2x DLA

2x PVA

2x DLA

2x PVA

? ?
Memory 8GB LPDDR4[59] 16GB LPDDR4[59] 16GB LPDDR4[51] 32GB LPDDR5 ? ?
Storage 64GB eMMC[59] 128GB eMMC[59] ? ?
Performance 4 FP32 TFLOPS

10-12 DL TOPS[60][61]

4 FP32 TFLOPS

10-12 DL TOPS [60][61]

16 FP16 TFLOPS

8 FP32 TFLOPS

20-24 DL TOPS [60][61]

4 FP32 TFLOPS

10-12 DL TOPS [60][61]

20 INT8 TOPS, 1.3 FP32 TFLOPS (GPU)
10 INT8 TOPS, 5 FP16 TFLOPS (DLA)[51] 		320 INT8 TOPS (total)[62] 400 INT8 TOPS (total) 2000 INT8 TOPS (total) 1000 INT8 TOPS[63] 2000 FP8 TOPS[47]
TDP 20W[61] 40W

SoC portion: 10W[43]

40W

SoC portion: 10W[43]

80W[64][65][61][66]

SoC portion: 20W[43]

60W[64][65][61]

SoC portion: 20W[43]

30W[51] 500W[62] 130W 750W ? ?

Note: dGPU and memory are stand-alone semiconductors; all other components, especially ARM cores, iGPU and DLA are integrated components of the listed main computing device(s)

References

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