Carbon nanotubes in interconnects

In nanotechnology, carbon nanotube interconnects refer to the proposed use of carbon nanotubes in the interconnects between the elements of an integrated circuit. Carbon nanotubes (CNTs) can be thought of as single atomic layer graphite sheets rolled up to form seamless cylinders. Depending on the direction on which they are rolled, CNTs can be semiconducting or metallic. Metallic carbon nanotubes have been identified^[1] as a possible interconnect material for the future technology generations and to replace copper interconnects. Electron transport can go over long nanotube lengths, 1 μm, enabling CNTs to carry very high currents (i.e. up to a current density of 10⁹ A∙cm⁻²) with essentially no heating due to nearly one dimensional electronic structure.^[2] Despite the current saturation in CNTs at high fields,^[2] the mitigation of such effects is possible due to encapsulated nanowires.^[3]

Carbon nanotubes for interconnects application in Integrated chips have been studied since 2001,^[4] however the extremely attractive performances of individual tubes are difficult to reach when they are assembled in large bundles necessary to make real via or lines in integrated chips. Two proposed approaches to overcome the to date limitations are either to make very tiny local connections that will be needed in future advanced chips or to make carbon metal composite structure that will be compatible with existing microelectronic processes.

Hybrid interconnects that employ CNT vias in tandem with copper interconnects may offer advantages in reliability and thermal-management.^[5] In 2016, the European Union has funded a four million euro project over three years to evaluate manufacturability and performance of composite interconnects employing both CNT and copper interconnects. The project named CONNECT (CarbON Nanotube compositE InterconneCTs)^[6] involves the joint efforts of seven European research and industry partners on fabrication techniques and processes to enable reliable carbon nanotubes for on-chip interconnects in ULSI microchip production.

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[MUSIC] So while we are doing the lecture is the demonstrate the different steps that we talked about, about process technology and We recall our use for, you know, demonstrating the different process steps is, is the microprocessor. So, last time we discussed whether the microprocessor is, is going to be the linchpin of semiconductor industry or not. Surprisingly, our answer was. Probably not, because we saw in a bit of material that, you know, other chips, the 4G LTE chips the communication chips were costing much more. And similarly if you see in your devices today most of the bottle necks you feel are not because of the processor being slow. Especially in a tablet or if your client is just. Manipulating [UNKNOWN] you don't need a very high, you don't need a very high end processor. But still it has very a lot of the leading edge steps in process technology take place. So this is the cross-section TM of the A6 microprocessor which came out a few weeks ago. And the Intel 22 nanometer [INAUDIBLE] . So, the, the first thing. Even just looking at it, the cross section look pretty different, right? So, uh,I would really reconsider, you can see, they have more granularity. [INAUDIBLE] , so you have multiple levels of interconnects. where as in an A6 microprocessor you only have a few pitches of your interconnects. So m1 to m4 are all the same pitch and m4 to m6 are all the same pitch and then the [UNKNOWN] above are also of similar pitch. So the reason is if you are change your pitch at every lithography step you have to optimize that lithography step you have to create a new mask You have to do all your optical proximity correction again. So, if, if you're not that worried about performance. You're probably are okay with that kind of interconnect where you have only three levels of pitches in your interconnect levels. So this is, you know, just by looking at the chips, they look different too. And if if you take out take out all the level of interconnects and take a photograph when you have removed all of the levels of interconnects. It looks something like this. This is a 6 transistor [UNKNOWN] cell If you take a cross-section view it would look something like this. This is a Even though it says Ivy bridge but there's still a 32 nanometer transistor. Uh,so you want to know is this transistor SRAM set. So it's, what I've done here and in the field of videos as well is actually list out. other transistors, often SRAM, set, so, SRAM set at [COUGH] roughly two of these inverters, cross connected to each other. So the gate of this is connected to the source in-drain of the other one. The gate of the first one is connected to the source in-drain of the other one. So essentially, two cross-connected interconnects as a flip-flop. So it will either be in the state zero, or if you flop it, it will be in the state one. And you have two other transistor, which are NMOS, which are essentially used to read or write state into the cells. So the way this is made out, is you have. these parallel lines, which are your gate lines, and these perpendicular lines, which are your active lines. And you always have two at least two or at least two p lines together. We'll see why that is the case. But you have at least adjacent active regions. For these two probably are p type and this is n type, and this one is n type too. I don't know how is it showing to you? I can't see that. It's much more clear over on my screen but. [LAUGH] So this, this is one of the gate lines, so these, this is running, connecting two of these transistors in the inverter. So you have NMOS there and PMOS there. And this gate is connecting to the source and drain of the other inverter. Similary, the gate of this inverter is connecting with the source and drain of this inverter. And then you have these two extra [UNKNOWN] that are pos-gate transistor. So this is the most, Efficient way to lay out a six transistor circuit. So this is why it's designed this way. It looks this way. in your problem sets you have one of the layouts which shows you eight transistor DRAM and you have to identify all the transistors there. Yeah? >> Is there a way to identify whether it's an NMOS or PMOS. >> Just by looking at it? >> Just by looking at it. >> So a cool tip which is that typically electron mobilities are twice that of full mobilities, right? So a active line for an NMOS is always wider, is always Thinner as compared to an active line for a PMOS. Because both of them need to have the same ohm of current, right? So if the mobility of this one, these two are lower, they need to be wider to support the same ohm of current. So you'll always find p lines to be wider, and n lines to be thinner. So that's one way to identify which one is p and which one is n, that's a good question. >> [SOUND]. So the first thing we need to start our process is, >> [COUGH]. >> We need some wafers, right? So the most common wafers. should I use our p type wafers. And they could either be bulk . Or you get these things which are called SOI wafers where you have a thin layer of silicon it, it is separated from this [UNKNOWN] wafer by this oxide layer. It's also called the, if this thin layer of silicon is less than ten nanometers, so it's also called E T S Y or Extremely thin is why. The company which makes a lot of this is [UNKNOWN] called SaiTech, they have a special process to make these wafers. The first step we do when we start is essentially we need to isolate our regions where we make. P-type transistors from the region where we make n-type transistors. So the first process step often then is isolation. We need to isolate the areas where we're going to be making PMOS from the area we are going to make NMOS. And the reason why it's nessecary is If you don't do that, you essentially have a region where you're making all your, all your NMOS transistors, which are [UNKNOWN] and [UNKNOWN]. And this is your PMOS transistor, which is [UNKNOWN] and [UNKNOWN]. So if you don't isolate with them, these are essentially below your transistor is the CMOS circutery battery. But if you look below you actually have a BGIT because you have this n, p, n, region here. And you have this p n p region over here, and these are cross connected. These are, again, the emitter here. Is connected to the base here, and the base here is connected to the emitter here. So these are cross If you don't isolate these p and n regions, then you'll get a latch-up phenomenon happening here. If if, some of you are E, a large majority of E, if you are not an E, just keep in mind what you need to do is isolate this p region from this n region. To avoid this latch-up. So [COUGH] the first step that you typically start your shallow trench isolation is you put outside in a nitride layer. And this is a very common material layer combination used where the nitride layer it's called a pad nitride. And it's a very common hard mask material. And By hard mask what I mean, it's, it's harder as compared to [UNKNOWN], Physically it's harder to etch as compared to So if you're going to to be etching things, if you're going to make [UNKNOWN] and etching features into your silicon. You would typically use a hard mask, which, essentially, is a material that does not etch. And it helps you form your feature. So nitrite is a very common hard mask. Sometimes people use an oxide layer. Not sometime. Almost all the times. People use an oxide layer below it. Because it helps in sticking. It also helps you reduce sticking another hard mask material we'll see later is ah,ti nitrite. Which is, again, a very difficult material to etch. So people use that as a hard mask [INAUDIBLE] . [UNKNOWN]. [COUGH] Then what do you do is, once you have your hard mask, you spin for this, for you [INAUDIBLE] this layer for others. I'm describing this process for once, we'll be repeating this again and again. So I want to make sure you understand the process of pardoning, and etching things the first time. And, so you [UNKNOWN] for a list and before a list start, these light sensitive organic materials. Which either form bonds or break bonds. Depending upon if you expose them with a high energy light. And if you have worked in a fab, you might have seen this equipment where you spray [UNKNOWN] and spin the wafer. And the layer, the thickness of the full resist is primarily depends upon how, how fast you spin your wafer. So the next step which is done is lithography, that is, you expose this to light and you make these patterns. many times, when you do in, in SNF. You don't, use, this thing called anti reflection coating. But most of the time, if you do it in an industrial lab below [INAUDIBLE] , you lose, you use anti reflective coating. Because you have. When you shine light you'll have reflection, light reflecting back from the surface too. And you'll a wide, a wide forming standing wave in this. [UNKNOWN]. So use a active anti anti-reflective coating And, just like it happened in a university fab after each critical process through, there's an inspection step. So, your list, there are others develop you inspect, if, if it's not okay, you rework your others. Right, so if your list okay, you again go to the next step, which is to form this isolation. So, essentially, this is a plasma etch step, or a dry etch step, also known as a reactive iron etch. And these are typically gases which are used, our highlighted gases are like bromine, fluorine. A fear for. The other common [UNKNOWN] which are gases which are for etching. And the reason they are used is that when they react with your material, your etching, that is silicon in this case. They form, in this case it will form CIBR4. Or CI. BR4 and that is a volatile component so it immediately goes away. And for things like silicon ox, or silicon oxide or aluminum we act, we are fortunate that we know gases or we know chemistry that can dry etch them. As we'll see later, most of the new materials which are being developed, right, we'll discuss later, like copper. People will put all kinds of materials in the periodic table into your microprocessor. But there are very few materials which the chemistry are known for. So. So that's why people prefer to use a [UNKNOWN] kind of process rather than an edge process because essentially the edge chemistries are not know. And I, I'll come to a [UNKNOWN] process in a few slides. But again after each step in this box is shown the inspection step, that is done so in this case, see when you etched it. You check whether you have the required profile so you do profilometry so you create a depth and you check your profile in wider trenches. Also this thing is called OCD or optical inspection of your depth profile. That's also a step we commonly use. once you have formed this feature, you fill it up. So you fill it up with an oxide. If it's a large-area feature, you can use any process you want, so you can use a high-density plasma. so as dimensions are shrinking and things, these aspect ratios of trenches you need to fill are getting higher and higher. So you need films which can, or you need very high density of plasma or you need films like Which you let a friend chemistry which can fill up this high aspect ratio. sometimes you use film which are flowable, so you fill them and a flow in and fill your feature. A good thing is that, when you make smaller feature, your capillary force actually goes higher. The capillary force is inversely proportional to the distance between all, it's inverse, it's inversely proportional to you're I think it's the third power of your feature size. So if you have a smaller filler. Your capillary forces, in fact increase and , so it tends to pull things inside. So that's one of the forces which is leveraged to fill, smaller features. So the next step you do after you fill the feature, you polish it, and, the process which is used is the CMP are chemical-mechanical Planner edition. This is one of the processes which causes a lot of your defects are caused from this process. Because even if you have one defect and the way CMP works is like a grinder. So even if you have one particle, it will grind all over your wafer. And so again was. Needed as an inspection step after you do this process. [COUGH] And then, you come and remove your hard mask, and then this guy's hard mask was nitride. So you can use the chemistry, like a phosphoric [INAUDIBLE] chemistry, which can remove your. Remove your nitride, it's very selective to nitride. So, again, after this you need to make sure that it's flat, so there's another inspection step. And then in this case it's a bright field inspection check, since we are checking for uniformity. So, the [INAUDIBLE] the point I'll emphasize are, the take home message here is that you need, with every process step, you need a inspection tool, so, The fastest and the most common inspection tools are based on, optical techniques. So, if you have worked in the [INAUDIBLE], you, I'm sure you, you know, you, every time you do a process, you go and check inside, you know. And look, look into a microscope, and look for you know, particles, or whether, if you're partening to form a list or not. And there are two kinds of microscopes. There's a dark-field microscope, and a bright-field microscope. the. The difference is shown very clearly here, so in a bright field, you essentially look in the field of view of your reflected light. So if it's a bright-field microscope, your, your detecting eye or your lens would be placed over here. If it's a dark field microscope, you look at, at it from a larger angle. Where you are not in the field of view of the light, of the reflected light. So, if you're looking for particles. So this is the question. So if you're looking for particles. Like, very small particles. the. If you are looking for particles, you want to look for scattering of light, so if you're looking for scattering of light, a better place to look is in the dark field. So if you're looking for particles, it's preferred to look in the dark-field microscope. If you're looking for, like, features like steps. Right? It's better to look in the bright-field microscope, they show up better. So a difference pattern show up better there, scattered pattern show up better in a, in a, in a dark-field microscope. So these are the same, I mean. There more sophisticated versions of this which are used in the industry but the operating principle is the same. You're looking at scattering or interference from your defects or your particles and your On your wafer. This works fine as long as your particles are bigger than the wavelength of light but what happens if they are smaller than the wave length of light. Or they are much, much smaller than the wave length of light. So then, then, what do we do? Most of the other Inspection tools they are based on this electron beams interacting with the wafer. And you might have used many of them while working [UNKNOWN] so this is you know the parade of how. How deep, you can inspect using different, different of these particles. So the most common of these are [INAUDIBLE]. Secondary electrons and, but they don't give you too much information of that. Another, common tool is this, uh,which utilizes back scattered electrons. Also contain the material information. So besides just telling you the defects, they also tell you the material of which your defect is made. Or the material of the film you're inspecting. And then deeper below are your xray particles. But this is the point I want to emphasis is that each process step you have inspection steps and. Increasingly as processes are becoming more and more complex, the number of process steps you have for inspection, they just keep on going up and up. [MUSIC]

Local interconnects

While smaller dimensions mean better performance for transistors thanks to the decrease of intrinsic transistor gate delay, the situation is quite the opposite for interconnects. Smaller cross-section areas of interconnect would only lead to performance degradation such as increased interconnect resistance and power consumption. Since the 1990s the circuit performance is no longer limited by the transistors, thus interconnects have become a key issue and are as important as the transistors in determining chip performance. As technology scaling continues, the problem of interconnect performance degradation will only become more significant. Local interconnects that are on the lower levels of the interconnect stack connecting nearby logic gates are aggressively scaled down at each generation to follow the miniaturization of transistors and thus are mostly susceptible to performance degradation. On the local level where interconnects are most densely packed, and have pitch sizes close to the minimum feature size, we will need new interconnect materials that suffer much less from sizing effects than copper.

Thanks to the measured properties of individual carbon nanotubes (CNTs), such material has been proposed as future material for interconnects.^[1] Particularly their current carrying capabilities are extremely high ^[4] typically around 10⁹ Acm⁻² and they exhibit a ballistic length up to micrometers.^[2] However, due to the strong electron-phonon interaction in single-walled CNTs, it has been discovered that electronic current undergoes saturation at the voltage bias beyond 0.2 V.^[2]^[3]

Nevertheless, CNTs with few nm in diameter are extremely robust compared with metallic nanowires of similar diameter and demonstrate conducting properties superior as compared with copper. To make a connection, CNTs have to be paralleled in order to lower the resistance.

The resistance R of one single-walled carbon nanotubes can be expressed by

R=R_{c}+R_{q}(1+L/L_{mfp})

Where $R_{c}$ is an extrinsic contact resistance, $R_{q}$ is the quantum resistance (6.5 kΩ) which comes from the connection of one dimensional material to a three dimensional metal, $L$ is the CNT length and $L_{mfp}$ is the mean free path of the electron. If N tubes are paralleled, this resistance is divided by N thus one of the technological challenge is to maximize N in a given area. If L is small as compared with L_mfp, which normally is the case for very small vias, the technological parameters to optimize are primarily the contact resistance and the tube density.

Initial works have been focused on CNT vias connecting two metallic lines. Low temperature (400 °C) chemical vapor deposition growth of CNT on titanium nitride catalysed by cobalt particles has been optimized by the Fujitsu group. The catalyst particles obtained by laser ablation of a cobalt target sorted by size ultimately allow to grow a CNT density around 10¹² CNT cm⁻² using a multistep process using plasma and catalyst particles around 4 nm. In spite of these efforts, the electrical resistance of such via is 34 Ω _for a 160 nm diameter. Performances are close to tungsten plugs thus at least one order of magnitude higher than copper. For 60 nm via, a ballistic length of 80 nm has been determined. For processing lines, CNT technology is more difficult because dense forests of CNTs naturally grow perpendicularly to the substrate, where they are known as vertically aligned carbon nanotube arrays. Only few reports on horizontal lines have been published and rely on the redirection of CNT,^[7]^[8] or the filling in existing trenches by fluidic assembly processes.^[9] The achieved performances are around 1 mΩcm, which is two decades higher than the requested values.

The reasons for such discrepancy between theoretical expectations and achieved performances are multiple. One obvious reason is the packing density after integration, which is far from the requested values, and the one used in the theoretical prediction. Indeed, even with the CNTs, which are strongly densified and spun, low conductance remains a problem. However, a recent paper ^[10] shows that a one-decade improvement on the conductivity may be gained just by high-pressure densification of the CNT. In spite of the development of high-density CNT material ^[11] the state of the art of integrated lines is still far from the 10¹³ cm⁻² conducting walls requested by the International Technology Roadmap for Semiconductors.^[12] Nevertheless, macroscopic assemblies with diameters of tens of microns consisting of double-walled CNTs ^[13] or single-walled carbon nanotubes ^[14] have experimental resistivity performances of 15 μΩcm after doping, demonstrating the potential of CNTs for interconnects.

Global interconnects

For current metallization technologies for high-performance and low-power microelectronics, copper is the material of choice due to its higher electromigration (EM) stability (resulting from the higher melting point) and conductivity to aluminium. For downscaled logic and memory applications up to 14 nm node the increased current density and reliability requirements per interconnect line still have known material and integration solutions. Thinner barrier and adhesion layers, doping of secondary metals to enhance grain boundary electromigration resistance, and integration concepts of selective cappings will be some of the adopted solutions. However, for dimensions below 7 to 10 nm nodes, the decreased volume of available conducting metal will force innovative material and integration approaches towards novel interconnect architectures. Also for power and high-performance applications the most critical challenges are high ampacity, thermal conductivity and electromigration resistance. Far away from bulk, copper conductors that would already melt at 10⁴ A/cm², current copper metallization lines can withstand 10⁷ A/cm² due to good heat dissipation into thermal contact to the surrounding material, optimized liner and capping as well as plating and CMP processes.

The reliability of state of the art interconnects is closely linked to electromigration . This adverse effect describes the material transport and consequently void formation especially in thin metal lines to the anode by a combination of the electron wind force, the temperature gradient induced force, the stress gradient induced force and the surface tension force. Depending on the design of the interconnect layout and the used metallization scheme, the dominance of each driving force can change. Even at the current scaling node of CMOS technology, these two issues are among the main reasons for the trend that the increased density scaling of transistors no longer automatically leads to "performance scaling" (i. e. increased performance per transistor).

CNTs are being studied as a potential copper replacement owing to their excellent electrical properties in terms of conductivity, ampacity and high frequency characteristics. However, the performances of CNTs integrated into functional devices are so far systematically much lower than those of nearly perfect CNTs selected for fundamental studies worldwide. As a consequence, combinations of CNTs with copper were envisioned soon after the pioneering study about CNT interconnects.^[15] Initial experimental realizations focused on a "bulk" approach where a mixture of CNTs and copper is deposited from a solution on the target substrate.^[16]^[17]^[18] This approach demonstrated mitigated performances for interconnect, such that focus is now almost exclusively on composite materials where the CNTs are aligned with respect to the current flow (referred to as aligned CNT-copper composite). Furthermore, contact resistance, mechanical stability, planarity and integration could be improved by a supporting conductive matrix. Chai et al.^[19]^[20]^[21] first demonstrated the fabrication of vertical interconnects using aligned CNT-copper composite materials in 2007 by first growing vertically aligned CNTs before filling the voids between CNTs with copper through an electroplating method. It was shown that this material could reach low, copper-like, resistivity but was more resistant to electromigration than copper. More recently, a renewed interest for this material was generated by the work of Hata group ^[22] claiming a 100 fold increase in current carrying capacity of aligned CNT-copper material compared to pure copper. Several groups are now working worldwide on the integration of aligned CNT-copper composite materials in interconnect structures,^[23]^[24]^[25]^[26] Present and near-future efforts are focusing on demonstrating and evaluating the performances of aligned CNT-copper composite materials for both vertical and horizontal interconnects, and to develop a CMOS-compatible process flow for multilevel global interconnects.^[6]

Physical and electrical characterization

Electromigration is typically characterized through the time of failure of a current carrying device.^[8] The scaling of the effect with current and temperature is used for accelerated testing and predictive analysis. Despite the great technological relevance of such measurements, there exists no widely used protocol to characterize electromigration. However, certain approaches are somewhat established, such as the variation of current and temperature. One of the unresolved challenges of electromigration are self-amplification effects of electromigration through self-heating at defects in interconnect leads.^[27] The local temperature rise due to current crowding across such defects is typically unknown. Since the underlying processes are typically thermally activated, the lack of precise knowledge of the local temperature makes the field of electromigration studies challenging, resulting in a lack of reproducibility and inter-comparability of different experimental approaches. A combination with in-situ temperature measurement is therefore desirable. There are numerous methods for thermometry and the measurement of thermal conductance of devices and structures on a length scale of microns to macroscopic. However, the quantitative thermal characterization of nanostructures is described as an unsolved challenge in the current scientific literature.^[28]^[29] Several methods have been proposed using Raman spectroscopy, electron energy loss spectroscopy, infrared microscopy, self-heating methods and scanning thermal microscopy. However, on the length scale relevant to single CNTs and their defects, i. e. the 1 nm-scale, no established solution exists applicable to CNT-based materials (our interconnects) and dielectrics (our insulators and matrix materials). Scanning thermal microscopy and thermometry ^[30] is the most promising technique for its versatility, but restrictions in tip fabrication, operation modes and signal sensitivity have limited the resolutions to 10 nm in the most cases. To increase the resolution of such technique is an open challenge which is attracting lot of attention from the industry and scientific community.^[6]

The methodology of electrical transport measurements in single CNTs, bundles and composites thereof is well established. To study finite-size effects in transport such as the transition from diffusive to ballistic transport requires the precise placement and addressing of nanoscale electrodes, typically fabricated using electron beam lithography.

Structural characterization of CNTs using transmission electron microscopy has been shown to be a useful method for structures identification and measures. Results have been reported with resolutions down to about 1 nm and very good material contact.^[31] Due to the experimental difficulties of contacting nano-objects inside an electron microscope, there have only been few attempts to combine transmission electron microscopy structural characterization with in-situ electrical transport measurements.^[32]^[33]^[6]

Modelling and simulation

Macroscopic

From a macroscopic point of view, a generalized compact RLC model for CNT interconnects can be depicted as in,^[34] where the model of an individual multi-wall carbon nanotube is shown with parasitics representing both dc conductance and high-frequency impedance i.e. inductance and capacitance effects. Multiple shells of a multi-wall carbon nanotube are presented by the individual parasitics of each shell. Such model can also be applicable to single-walled carbon nanotubes where only a single shell is represented.

The shell resistance of an individual nanotube can be obtained by computing the resistance of each shell as

R_{shell}=R_{i}+R_{c}+R_{hb}+R_{o}

where $R_{i}$ is the ballistic resistance, $R_{c}$ is contact resistance, $R_{o}$ is the distributed ohmic resistance and $R_{hb}$ is the resistance due to the applied bias voltage. Capacitance of nanotubes consists of quantum, C_q and electrostatic capacitance C_e. For multi-wall carbon nanotubes, there is the shell-to-shell coupling capacitance, C_c. Additionally there is a coupling capacitance, C_cm between any two CNT bundles. As for inductance, CNTs have both kinetic, L_k and magnetic inductance, L_m. There are also mutual inductances between shells, M_m and bundles, M_mm.

Detailed simulation for signal interconnects have been performed by Naeemi et al.,^[35]^[36]^[37] and it has been shown that CNTs have lower parasitics than copper metal lines, however, the contact resistance between CNT-to-CNT and CNT-to-metal is large and can be detrimental for timing issues. Simulation of power delivery interconnects performed by Todri-Sanial et al.^[38] have shown that CNTs overall lead to reduced voltage drop compared with copper interconnects.

The significant dependence of the current density between the CNTs on the geometry between them has been proved by Tsagarakis and Xanthakis.^[39]

Mesoscopic

The macroscopic circuit simulation addresses just the interconnect performance neglecting other important aspects like reliability and variability of CNTs, which can be properly treated only at mesoscopic level by means of fully three dimensional Technology Computer Aided Design modelling approaches.^[40] Recently, industrial and scientific community are investing considerable efforts to investigate the modelling of CNT variability and reliability by means of three dimensional Technology Computer Aided Design approaches for advanced technological generations.^[6]

Microscopic

Underneath the macroscopic (Circuit Level) and mesoscopic (Technology Computer Aided Design level) modelling of CNT interconnects, it is also important to consider the microscopic (Ab Initio level) modelling. Significant work has been carried out on the electronic,^[41]^[42]^[43]^[44] and thermal,^[45]^[46] modeling of CNTs. Band structure and molecular level simulation tools can be also found on nanoHUB. Further potential modeling improvements include the self-consistent simulation of the interaction between electronic and thermal transport in CNTs, but also in copper-CNT composite lines and CNT contacts with metals and other relevant materials.

The CNTs with encapsulated nanowires have been studied at the ab initio level with self-consistent treatment of electronic and phonon transport and demonstrated to improve current-voltage performance.^[3]

A fully experimentally-calibrated electrothermal modelling tool would prove useful in studying, not only the performance of CNT and composite lines, but also their reliability and variability, and the impact of the contacts on the electronic and thermal performance.^[6] In this context, a full three dimensional physics-based and multi-scale (from ab-initio material simulation up to circuit simulation) simulation package that takes into account all aspects of VLSI interconnects (performance, power dissipation and reliability) is desirable to enable accurate evaluation of future CNT-based technologies.

References

^ ^a ^b Kreupl, F; Graham, A.P; Duesberg, G.S; Steinhögl, W; Liebau, M; Unger, E; Hönlein, W (2002). "Carbon nanotubes in interconnect applications". Microelectronic Engineering. 64 (1–4). Elsevier BV: 399–408. arXiv:cond-mat/0412537. doi:10.1016/s0167-9317(02)00814-6. ISSN 0167-9317.
^ ^a ^b ^c ^d Park, Ji-Yong; Rosenblatt, Sami; Yaish, Yuval; Sazonova, Vera; Üstünel, Hande; Braig, Stephan; Arias, T. A.; Brouwer, Piet W.; McEuen, Paul L. (2004). "Electron−Phonon Scattering in Metallic Single-Walled Carbon Nanotubes". Nano Letters. 4 (3). American Chemical Society (ACS): 517–520. arXiv:cond-mat/0309641. Bibcode:2004NanoL...4..517P. doi:10.1021/nl035258c. ISSN 1530-6984. S2CID 32640167.
^ ^a ^b ^c Vasylenko, Andrij; Wynn, Jamie; Medeiros, Paulo V. C.; Morris, Andrew J.; Sloan, Jeremy; Quigley, David (2017-03-27). "Encapsulated nanowires: Boosting electronic transport in carbon nanotubes". Physical Review B. 95 (12): 121408. arXiv:1611.04867. Bibcode:2017PhRvB..95l1408V. doi:10.1103/PhysRevB.95.121408. S2CID 59023024.
^ ^a ^b Wei, B. Q.; Vajtai, R.; Ajayan, P. M. (20 August 2001). "Reliability and current carrying capacity of carbon nanotubes". Applied Physics Letters. 79 (8). AIP Publishing: 1172–1174. Bibcode:2001ApPhL..79.1172W. doi:10.1063/1.1396632. ISSN 0003-6951.
^ Chai, Yang; Chan, Philip C. H. (2008). "High electromigration-resistant copper/carbon nanotube composite for interconnect application". 2008 IEEE International Electron Devices Meeting. IEEE. pp. 1–4. doi:10.1109/iedm.2008.4796764. ISBN 978-1-4244-2377-4.
^ ^a ^b ^c ^d ^e ^f "CORDIS | European Commission".
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